1. Field of the Invention
Embodiments of the invention relate to a Complementary Metal Oxide Semiconductor (CMOS) transistor and a related method of manufacture. More particularly, embodiments of the invention relate to a CMOS transistor formed from a simplified manufacturing process yielding simultaneous improvements in the performance properties of first and second conductivity type MOS transistors, and a related method of manufacture.
This application claims priority to Korean Patent Application No. 10-2005-0016722 filed on Feb. 28, 2005, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
As semiconductor devices have become more highly integrated, the length of the gate in constituent MOS transistor has been progressively reduced. As the gate length in MOS transistors has been reduced, the effective length of the corresponding channel region for the MOS transistors has also been reduced. As the length of the channel region in MOS transistors is reduced, the effect of the source/drain region(s) on the electric field (or voltage potential) associated with the channel region increases. This result is referred to as the “short channel effect.” The negative performance impact of the short channel effect is particularly pronounced in PMOS transistors.
Thus, a variety of methods have been proposed to improve the performance of MOS transistors having reduced gate (and channel) lengths. Among these are methods that create a strain in order to increase mobility of electrical carriers (e.g., electrons and/or holes) by applying a tensile or compressive force to the channel region below the gate.
Representative of methods of creating strain is one method in which a tensile force is generated in the channel region of an NMOS transistor by varying the type and thickness of a layer acting as an etch stop layer during a process step(s) adapted to form a contact hole. In another method, the source/drain region of a PMOS transistor is recessed, and then the recessed region is filled with silicon germanium (SiGe). Since SiGe has a larger lattice constant than silicon (Si), which has a lattice constant of 5.43 Å, the in-fill of SiGe using a selective epitaxial growth (SEG) technique will generate a compressive force in the channel region. This type of method is disclosed, for example, by T. Ghani, M. Armstrong, et al., in an article entitled “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors,” (IEEE, 2003).
Thus, generally speaking, one type of strain is effective in the creation of a strain in NMOS transistors while another type of strain is effective in the creation of strain in PMOS transistors. That is, the performance properties of the respective channel regions in NMOS and PMOS transistors react differently to different strain types (e.g., compressive or tensile). However, a CMOS transistor structure comprises both NMOS and PMOS transistors. Thus, application of one remedy intended to improve the performance of the channel region in a PMOS transistor may actually impair the performance of the channel region in the NMOS transistor, and vice verses.